1. Field of the Invention
The present invention relates to successive approximation analog-to-digital signal converters (SAR ADCs), and in particular, to capacitor arrays forming the digital-to-analog converter (DAC) portion of an SAR ADC.
2. Description of the Related Art
Referring to FIG. 1, a conventional SAR ADC implemented with an array of capacitors for the DAC portion includes a DAC 12, voltage comparator 14, and SAR logic 16, interconnected as shown. The analog input V.sub.IN is processed, i.e., weighted, within the DAC 12 in accordance with the digital data bits 17 from the SAR logic 16. This produces an analog voltage at output 13 which is compared to a reference voltage V.sub.CR by the comparator 14. The comparator output 15 is processed by the SAR logic 16 in accordance with well known principles to produce the digital output data bits 17.
Using a capacitor array-based DAC, as opposed to a resistive ladder network (the analog output of which is compared against the analog input V.sub.IN by the comparator), provides several advantages, such as no DC power dissipation, no static current drain through switches, plus good matching between the passive components, i.e., the capacitors.
Referring to FIG. 2, a conventional implementation of the capacitor array 12a within the DAC 12 uses binary weighted capacitor values. During the sampling phase, each of the capacitors C.sub.0, C.sub.1, C.sub.2, . . . , C.sub.N-1 within the array is driven by the analog input V.sub.IN, while during the hold phase, i.e., the successive approximation conversion phase, each capacitor is individually driven by a reference voltage V.sub.REF which is weighted with one of the input data bits D.sub.K.
Referring to FIG. 3, operation of the conventional binary capacitor array can be better understood. In addition to the capacitor array 12a itself, the DAC 12 also includes a switching matrix 12b which includes N switches S.sub.0, S.sub.1, S.sub.2 . . . , S.sub.N-1 (where N equals the number of digital data bits 17) and controls the driving of the individual capacitors C.sub.0, C.sub.1, C.sub.2, . . . , C.sub.N-1. During the sampling phase, the switch S across the inputs of the comparator 14, in accordance with a sample and hold control signal S/H, is closed and the input switches S.sub.0 -S.sub.N-1 are in position 1, thereby causing the capacitors to be driven by the analog input V.sub.IN. During the hold phase, the switch S across the inputs of the comparator 14, in accordance with the control signal S/H, is opened and each of the individual input switches S.sub.0 -S.sub.N-1, in accordance with its respective digital data signal bit D.sub.0 -D.sub.N-1, is switched into position 2 or 3. For example, for the first input switch S.sub.0, if its data bit D.sub.0 is a logic 0, the switch S.sub.0 is in position 2, while if the data bit D.sub.0 is a logic 1, the switch S.sub.0 is in position 3. Accordingly, the inputs to each of the capacitors C.sub.0 -C.sub.N-1 is a binary weighted version of the reference voltage V.sub.REF.
Notwithstanding the aforementioned advantages of a capacitor array-based DAC, however, such an implementation has a significant disadvantage. In order to provide good matching of the capacitors, the larger capacitors are constructed using multiples of a selected unit capacitance. However, for the implementation as shown in FIGS. 2 and 3, the ratio of the larger capacitor to the smallest capacitor increases exponentially with the number of bits. This increases the area needed for the capacitor array, as well as the input capacitance during the sampling phase of operation. For example, the input capacitance for such implementation during the sampling phase is the sum of the capacitances of all of the input capacitors C.sub.0 -C.sub.N-1 (i.e., C+2C+4C+ . . . +2.sup.N-1 .multidot.C).
Referring to FIG. 4, one conventional technique used to reduce the necessary area for the capacitor array, as well as reduce the large input capacitance during the sampling phase, is to use a split capacitor array. In such a DAC 12c which uses such an array, a coupling capacitor C.sub.C essentially splits the array into two smaller capacitor arrays. Operation of the primary input switches S.sub.0 -S.sub.K+M for driving the primary input capacitors C.sub.0 -C.sub.K+M (where K+M=N) is as described above in connection with the DAC 12b of FIG. 3. One additional input capacitor C.sub.S, driven by the sample and hold control signal S/H, is also used, along with a corresponding switch S.sub.S which is switched into position 1 during the sampling phase and is switched into position 2 during the hold phase. The areas of the necessary capacitors are reduced because of the reduced maximum capacitor value within each of the smaller capacitor arrays on either side of the coupling capacitor C.sub.C.
However, a significant disadvantage of this technique is the fractional value of the coupling capacitor C.sub.C used to split the overall capacitor array. Having such a fractional value results in poor matching between the coupling capacitor C.sub.C and the remaining individual capacitors C.sub.S, C.sub.0 -C.sub.K, C.sub.K+1 -C.sub.K+M within the array. While it is possible to improve this matching by appropriately ratioing the area and perimeter of the coupling capacitor C.sub.C to the area and perimeter of the unit capacitors C.sub.S, C.sub.0 -C.sub.K, C.sub.K+1 -C.sub.K+M, this makes the layout of the array more difficult to achieve. Further, any mismatch between the fractional coupling capacitor C.sub.C and the remaining capacitors C.sub.S, C.sub.0 -C.sub.K, C.sub.K+1 -C.sub.K+M affects the overall performance of the converter 12c in terms of its differential non-linearity.
Accordingly, it would be desirable to have an implementation of a capacitor array-based DAC which avoids problems associated with capacitors which increase exponentially in size with the number of bits, while also avoiding problems associated with matching between unit and fractional value capacitors.